数字逻辑设计对Verilog使用的记录

wire [2:0]w_p0, w_p1, w_p2, w_p3, w_p4, w_p5, w_p6, w_p7, w_p8;
reg [2:0]r_p0 = 0, r_p1 = 0, r_p2 = 0, r_p3 = 0, r_p4 = 0, r_p5 = 0, r_p6 = 0, r_p7 = 0, r_p8 = 0;
reg count = 1;

//连续赋值将wire变量设置为对应的reg变量的值
assign w_p0 = r_p0;
assign w_p1 = r_p1;
assign w_p2 = r_p2;
assign w_p3 = r_p3;
assign w_p4 = r_p4;
assign w_p5 = r_p5;
assign w_p6 = r_p6;
assign w_p7 = r_p7;
assign w_p8 = r_p8;

setqi a1(.count(count), .sw(sw), .p0(w_p0), .p1(w_p1), .p2(w_p2), .p3(w_p3), .p4(w_p4), .p5(w_p5), .p6(w_p6), .p7(w_p7), .p8(w_p8), .stop(stop));

always @(posedge stop)
begin
    r_p0 <= 0; r_p1 <= 0; r_p2 <= 0; r_p3 <= 0; r_p4 <= 0; r_p5 <= 0; r_p6 <= 0; r_p7 <= 0; r_p8 <= 0; //进行清零操作
    //引入vga图片显示game over
end

取反操作
module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out={in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule
//如果为 assign out[7:0]=in[0:7] 会报错

矢量亦可以复制
{5{1'b1}}           // 5'b11111 (or 5'd31 or 5'h1f)
{2{a,b,c}}          // The same as {a,b,c,a,b,c}
{3'd5, {2{3'd6}}}   // 9'b101_110_110. It's a concatenation of 101 with
                    // the second vector, which is two copies of 3'b110.
module top_module (
    input [7:0] in,
    output [31:0] out );//

    // assign out = { replicate-sign-bit , the-input };
    assign out={ {24{in[7]}},in};
endmodule//括号一定不能少打

多个复制问题
module top_module (
    input a, b, c, d, e,
    output [24:0] out );//
    // The output is XNOR of two vectors created by 
    // concatenating and replicating the five inputs.
    // assign out = ~{ ... } ^ { ... };
    assign out=~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{5{a,b,c,d,e}}; 
endmodule

多模块以及选择器:(模块一定要注意对应位置不要出错，太关键了)
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] q1,q2,q3;
    my_dff8 a1(clk,d,q1);
    my_dff8 a2(clk,q1,q2);
    my_dff8 a3(clk,q2,q3);
    always @(*) begin
        case(sel)
            2'b00:q=d;
            2'b01:q=q1;
            2'b10:q=q2;
            default:q=q3;
        endcase
    end
endmodule

分线与加法器
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15:0] sum1,sum2;
    wire cout1,cout2;
    add16 a1(a[15:0],b[15:0],0,sum1,cout1);
    add16 a2(a[31:16],b[31:16],cout1,sum2,cout2);
    assign sum={sum2,sum1};
endmodule

简单加法器
module add1 ( input a, input b, input cin,   output sum, output cout );
assign sum=a^b^cin;
    assign cout=(a & b) | (b & cin) | (cin & a);
// Full adder module here

endmodule

加减法 需要注意的是按位与必须两者都要相同位数，则需要进行复制操作
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire [31:0] b1;
    wire [15:0] sum1,sum2;
    wire cout1,cout2;
    assign b1=b^{32{sub}};
    add16 a1(a[15:0],b1[15:0],sub,sum1,cout1);
    add16 a2(a[31:16],b1[31:16],cout1,sum2,cout2);
    assign sum={sum2,sum1};
endmodule

if语句运用 需要注意的是寄存器必须改变状态
// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
            shut_off_computer=0;
    end

    always @(*) begin
        if (~arrived&&~gas_tank_empty)
           keep_driving = 1;
        else
            keep_driving=0;
    end

endmodule